The present invention is directed to frequency-shift keyed (FSK) demodulating circuits and more specifically to an adaptive digital demodulating circuit.
Frequency-shift keyed signals are found in a variety of applications involving data transmission such as RF transmissions and telephone data transmission. FSK signals use two distinct frequencies to represent logic level "1" signal and the logic level "0" signals. A demodulating circuit converts the frequency data to a digital format for use in associated circuitry.
Several techniques are known for demodulating FSK signals. One method described in U.S. Pat. No. 4,574,247 requires the derivation of a reference signal from a full data signal train that requires both the "1" and "0" frequencies to be present. The two frequencies must be present for a relatively large amount of time to set a reference before data reception. The reference value obtained represents a frequency between the logic 0 value and the logic 1 value. One disadvantage of the circuit is that noise contained in the input signal causes the reference to be set incorrectly.
Other methods of demodulating an FSK signal use a phase lock loop to provide feedback. One drawback to such circuits is the high cost due to the high number of components. Another disadvantage is that during the manufacturing process the phase lock loop requires calibration. Such circuits are not easily manufacturable on a single integrated circuit.
It would be desirable to provide a low cost, low part count circuit that can be fabricated on one integrated circuit to reliably demodulate an FSK signal.